Super-Kamiokande

at Boston University

Trigger Module Development

• A Brief Description of the daughtercard operation.
• Rev B Daughtercard Schematic GIF file or Postscript, suitable for printing
• Rev C PAL equations (PALCE16V8Q-10)
• Some Notes on using the MQT200F charge-to-time converter chip from LeCroy
• Proposed Specifications for the module
• Preliminary Block Diagram
• Timing Diagram
• Linearity Plot from our prototype PC board
• Integral Non-Linearity using LeCroy 2249 CAMAC ADC for reference
• Development status
• Schedule

Other Super-K work at BU

and Elsewhere

• Super-K page at University of Washington and
• Super-K page at University of Hawaii

Miscellany

Maxim max9686 Data Sheet

Motorola MJ11029 power transistor data sheets
GIF
PostScript