A block diagram of the daughtercard is shown here. A discriminator, set at a fraction of a pe equivalent pulse height, senses input pulses. The discriminator output triggers a one-shot circuit which produces a gate for the LeCroy MQT200F charge-to-time converter. The raw discriminator output is combined with the MQT output to form a pulse train, giving time-over-threshold and pulse count information pulse the total charge.
A timing diagram is shown below. The design is complicated somewhat by
the need to prevent re-triggering while the MQT output is active, and
the desire to provide several different modes of operation.
The logic controlling daughtercard operation is contained within a
16V8 type PAL (programmable array logic) device. An equivalent circuit
to the PAL (used for simulation purposes) is shown below. In the middle
of the diagram are two blocks surrounded by dotted lines; these
represent two one-shot timers which generate the gate and an additional
delay to provide a gap before the start of the charge pulse. The
one-shot circuits are not actually included on the PAL; they are
implemented using an external dual flip-flop IC.
Briefly, the PAL logic operates as follows. A large 'OR' gate (functioning as an 'AND' for inverted logic) triggers the two one-shots when several conditions are met:
The MQT200F "TIME" output (proportional to charge) occurs after a fixed delay from the beginning of the GATE input, and inconveniently this delay is about 200ns. Thus, a tricky bit of logic is required to ensure that the Q pulse output by the daughtercard begins at the end of the 2nd one-shot period and ends when the MQT200F "TIME" output ends. This is implemented as a simple RS flip-flop using two NAND gates on the PAL, shown in the lower-right part of the diagram.
Two special modes of operation are available.