TITLE Super-K trigger module front-end PATTERN bart4.pds REVISION A AUTHOR E. Hazen COMPANY Boston University DATE 12-18-95 ; ; Mods: ; Bart1 - initial version; various problems ; Bart2_s - simulation (only) version as 22V10 ; Bart2 - ok, but IQ/IQN FF latches up on power-up ; or if TIME never comes ; Bart3 - get rid of IQ term in T1, T2 (temporary fix) ; side effect: FF's can re-trigger between gate end and TIME start ; Bart4 - use one-shot (Q1) as veto for inputs, set long enough for ; TIME leading edge delay. Insert additional R-C delay from Q2 to ; new QD input, use overlap to generat reasonable width T pulse ; in non-TOT mode. TOT mode is OK, but T pulses may occur right ; up to the start of the Q pulse, which could be confusing in software. CHIP bart1_A PALCE16V8 ; Pin assignments ; 1 2 3 4 5 6 7 8 9 10 NC /PMT VETO NTOT TEST QONLY QD NC TIME GND ; 11 12 13 14 15 16 17 18 19 20 NC T1 Q1 T2 Q2 IQ IQN TRIG TQOUT VCC EQUATIONS ; T1 and T2 are the clocks for the two 1-shots (they are identical) ; make them a short pulse triggered on the PMT input or TEST input T1 = (/TIME * PMT * /Q1 * /Q2 * /VETO) + ; VETO disables PMT input (/TIME * TEST * /Q1 * /Q2) ; TEST works with or without VETO T2 = (/TIME * PMT * /Q1 * /Q2 * /VETO) + ; VETO disables PMT input (/TIME * TEST * /Q1 * /Q2) ; TEST works with or without VETO ; make an RS flip-flop. We need this to generate the "Q" output, ; which starts at the end of gate, and ends at the end of TIME ; IQ and IQN are the Q and /Q outputs of the RS flip-flop ; Q2 (GATE) is active-low S input ; TIME is active-low R input IQ = /(IQN * /Q2) IQN = /(IQ * /TIME) ; make the final output pulse which goes to the TDC ; there are two terms OR'd to make this pulse ; the first is the "TOT" pulse, which is either: ; Q1 only (if NTOT is high) or ; PMT gated by Q1 (if NTOT is low) ; the second is the "Q" pulse, which is ; (IQ * /Q2) + TIME TQOUT = ( (/QONLY * ( (NTOT*Q2*/QD) + (/NTOT*Q2*((PMT*/VETO)+TEST)))) + (/Q2 * /(IQN*/TIME)) ) TRIG = Q2